Semiconductor devices have traditionally been fabricated on a monocrystalline silicon layer. The manufacture and orientation of semiconductor crystals is well known in the art and is discussed in many articles and books including Microelectronics Processing and Device Design by Colclaser and VLSI Technology edited by Sze which are herein incorporated by reference and referred to as Colclaser and Sze, respectively. A silicon crystal has a basic tetrahedral structure that forms a diamond lattice. A silicon crystal ingot is formed from a seed crystal such that when the ingot is formed and subsequently lapped into wafers. A wafer's exposed surface, which will be used to subsequently form devices, lies generally along a (100) crystal plane, (110) crystal plane, or (111) crystal plane. Many metal oxide semiconductor (MOS) devices are made from wafers having an exposed (100) crystal plane. The (100) family of crystal planes consists of the (100), (010), (001), (100), (010), and (001) crystal planes and are all equivalent planes which are hereinafter referred to as the (100 ) crystal planes. A bar over a "1" indicates a negative number. Perpendicular to each of the (100) crystal planes are directions including &lt;100&gt;, &lt;010&gt;, &lt;001&gt;, &lt;100&gt;, &lt;010&gt;, and &lt;001&gt; and hereinafter are referred to as the &lt;100&gt; crystal directions. Similarly, there are the (110) and (111) families of crystal planes with their corresponding crystal directions that are herein referred to as the &lt;110&gt; crystal directions and the &lt;111&gt; crystal directions, respectively.
Many monocrystalline silicon wafers have an exposed surface generally lying along a (100) crystal plane and are herein referred to as (100) wafers. During formation of a wafer, at least one flat is typically formed along the edge of the wafer. The wafer may have more than one flat as shown in FIG. 24 on page 35 of Sze. If there is more than one flat, the longest flat is generally referred to as the primary flat. Within the semiconductor industry, the primary flat typically lies along a &lt;110&gt; crystal direction for (100) wafers. Cleavage planes for (100) wafers fall along the &lt;110&gt; crystal directions of the (100) crystal plane. The significance of the cleavage planes is discussed below.
A (100) wafer is subjected to a number of processing steps used to form devices within the wafer. During the fabrication of the devices, the first masking layer is typically aligned to the primary flat. The devices are usually rectangular and have rectilinear circuit patterns to keep wasted area to a minimum. Therefore, the borders of the devices and a significant fraction of the edges of the circuit patterns typically lie along the &lt;110&gt; crystal directions (cleavage planes). The wafer including finished devices is subjected to various packaging steps that take the devices from wafer form and put the device into individual packages. One of the operations during this packaging sequence is the sawing of the wafer into the individual devices. The prior art places the borders of the devices along the cleavage planes because the wafer breaks easier along the cleavage planes compared to directions other than along the cleavage planes which is why prior art devices are oriented primarily along the cleavage planes.
Crystal lattices may have three types of crystal defects: point defects, dislocation defects (also called line defects), and planar defects. The formation of a field oxide layer typically exerts a great amount of stress on the crystal lattice at field oxide-active area edges. For prior art devices, the field oxide-active area edges typically fall along the &lt;110&gt; crystal directions (cleavage planes) because the rectilinear circuits patterns are aligned to the primary flat, which falls along a cleavage plane. Therefore, dislocation defects along the field oxide-active area edges easily form during a field oxidation step because the prior art methods orient the field oxide-active area edges along the cleavage planes.
During the fabrication of metal oxide semiconductor devices, a gate electrode, which is typically comprised of polycrystalline silicon, is typically perpendicular to the field oxide-active area edge. Therefore, the gate electrodes generally are oriented along the cleavage planes, too. Device parameters include transistor length, which is the distance between the source tip region and drain tip region under the gate electrode, and transistor width, which is perpendicular to the transistor length. The transistor length is also called the effective channel length. A gate electrode that crosses an active area may be narrow enough such that the dislocation defect is longer than the transistor length thereby forming a "leaky" device. The device is considered leaky if the drain current is above a predetermined amount, such as 100 nA, when the source and gate are grounded and the drain is at a potential of about 5 V. The actual drain current used to determine whether or not a device is leaky varies according to the circuit design and density and varies according to one's circuit specifications.
State of the art devices within the semiconductor industry are currently fabricated using technologies having their smallest patterned dimension of about 0.8 .mu.m. Future generations of devices are currently being designed with patterned dimensions of about 0.6 .mu.m and smaller. The length of a dislocation defect along a cleavage plane needed to form a leaky device is its smallest when the field oxide-active area edge and the gate electrode are oriented primarily along the cleavage planes. The prior art method of orienting devices primarily along the cleavage planes has a greater likelihood of forming a 0.6 .mu.m device with a dislocation-related leakage failure than a 0.6 .mu.m device formed in accordance with the present invention described below.
The problems with the prior art have been described with reference to (100) wafers having devices and circuit patterns oriented substantially along the cleavage planes. Similar problems are expected whenever devices are oriented substantially along the cleavage planes for other types of monocrystalline substrates including germanium, silicon, gallium arsenide, etc. regardless of crystal plane orientation of the exposed substrate surface for any of these materials. Although the cleavage planes for (100) wafers fall along the &lt;110&gt; directions, the cleavage planes for other types of substrates may fall along the same or different crystal directions.